According to U.S. Pat. No. 6,556,934, signal propagation times TA1, TA2, TA3 . . . of respective pin selection paths of a pin selection device that selectively connects output pins of a semiconductor device testing apparatus to a timing measurement device are measured in advance, and the measured values are memorized. At the time of timing calibration, calibration pulses are transmitted to a timing calibrators via respective test pattern signal transmission paths and respective pin selection paths to measure delay time values T1, T2, T3, - - - of respective channels, The known values TA1, TA2, TA3 , - - - are subtracted from the measured values T1, T2, T3, - - - , respectively. A timing calibration is performed by adjusting delay time values of the timing calibrators of the respective test pattern signal transmission paths such that each of the respective differences between the TA1, TA2, TA3, - - - and the measured values T1, T2, T3, - - - become a constant value TC.
Testing the clock timing of read and/or write addressing functions of a memory module is useful to determine if the timing settings need to be retimed to assure the device being tested is in an operational mode with no failure in clock timing. Previous solutions for retiming have included: switchable timing paths of different time domains, which are either hardwire or printed circuits external to the memory module, or redundant input/output pins on a clock or on a memory for switchable selection of such pins to select different timing paths in the clock or in the memory. Alternatively, retiming has been provided by digital phase lock loop (DPLL) feedback controls to retime the address functions and eliminate time domain drift. Such retiming solutions are inefficient for consuming high operating power and semiconductor real estate, and at times has required manufacturing retooling of the semiconductor devices.
Retiming of the read and/or write addressing functions is desirable to obtain optimum timing performance for each clock path. Further, a tuning operation is desirable to shift the retimed performance to the center of a range of permissible performances. Without such tuning, even a slight shift in timing performance (which may be caused by semiconductor processing, ambient atmospheric and applied voltage disturbances) would shift the performance outside of a permissible range, and thereby cause a timing performance failure.